1. Field of the Invention
The present invention relates to a power-on detecting circuit for detecting application of power to an electronic circuit device.
2. Description of the Background Art
In various electronic circuit devices, it is necessary to internally initialize circuit devices upon power-on. For this purpose, there have been used power-on detecting circuits which monitor power supply potentials and generate signals indicating the power-on when the power is applied.
FIG. 11 schematically shows a construction of a general electronic circuit device. In FIG. 11, the electronic circuit device (will be called merely "semiconductor device" hereinafter) 500 includes an internal circuit 510 for carrying out a predetermined function, a power-on detecting circuit 520 which monitors a power supply potential applied to a power application node (or power terminal) 550 and generates a power-on detection signal /POR indicating the power-on when the power is applied, and an initializing circuit 530 which is responsive to power-on detection signal /POR to initialize or reset internal circuit 510.
Internal circuit 510 may be any circuit device such as a semiconductor memory device or logical processing device. Power-on detecting circuit 520 generates power-on detection signal /POR when the power supply potential applied to power application node 550 rises to a predetermined potential. Initializing circuit 530 is activated in response to a state transition (i.e., rise or fall) of power-on detection signal /POR and initializes or resets a predetermined circuit portion in internal circuit 510.
The initialization of internal circuit 510 upon the power-on enables a stable operation of semiconductor device 500 when it carries out the intended processing thereafter.
FIG. 12 shows an example of a construction of the power-on detecting circuit in the prior art. Referring to FIG. 12, power-on detecting circuit 520 includes a capacitance 1 for achieving capacitive coupling between a power line 55 and a node ND1, an inverter circuit 3 for inverting a potential of node ND1, an inverter circuit 2 for inverting and transmitting an output of inverter circuit 3 to node ND1, an inverter circuit 4 for inverting the output of inverter circuit 3, and an inverter circuit 5 for inverting an output of inverter circuit 4 and generating power-on detection signal /POR.
The capacitance 1 monitors a power supply potential VCC transmitted to power line 55, and responds to the rise of power supply potential VCC at the power-on by rising the potential of node ND1.
Inverter circuits 2 and 3 form a latch circuit, which latches the potential of node ND1 and stably generates the signal indicating the power-on.
Inverter circuit 3 includes p-channel MOS (insulated gate type field effect) transistors P1 and P2 which receive the potential of node ND1 at respective gates, and n-channel MOS transistors N1 and N3 which receive the potential of node ND1 at respective gates. Transistors P1, P2, N1 and N3 are complementarily connected between power supply potential VCC and the ground potential. Inverter circuit 3 further includes a p-channel MOS transistor P3 disposed in parallel to p-channel MOS transistor P2 for receiving the output of inverter circuit 4 at its gate, and an n-channel MOS transistor N2 disposed in parallel to n-channel MOS transistor N1 for receiving the output of inverter circuit 4 at its gate.
Power-on detecting circuit 520 further includes a capacitance 7 disposed between an output node ND5 of inverter circuit 3 and the ground potential, a delay circuit 8 which responds to the output of inverter circuit 5 and generates a reset signal after a predetermined time elapses, and a reset circuit 6 which responds to the output of delay circuit 8 by resetting the potential of node ND1 to the ground potential, Capacitance 7 slows the rise of the potential at output node ND5 of inverter circuit 3, whereby the latch capability of the latch circuit formed of inverter circuits 2 and 3 is weakened upon the power-on.
Delay circuit 8 includes a p-channel MOS transistor P4 and an n-channel MOS transistor N8 which receive the output of inverter circuit 5 at their gates, a p-channel MOS transistor P6 which is disposed between one conduction terminal of transistor P4 and a node ND3 and has a gate connected to the ground potential, an n-channel MOS transistor N10 disposed between node ND3 and output node ND4 of delay circuit 8, and an n-channel MOS transistor N12 which is responsive to the output of inverter circuit 5 to electrically connect node ND4 to the ground potential. Transistor P6 is normally in the on-state and functions as a resistor. Transistor N10 has a gate and a drain connected together, and functions as a resistor. Transistor N12 sets node ND4 at the ground potential level when power-on detection signal /POR rises to the high level.
Reset circuit 6 includes an n-channel MOS transistor N6, which receives the output of delay circuit 8 at its gate and electrically connects node ND1 to the ground potential.
Delay circuit 8 transmits the signal at the high level to node ND4 when power-on detection signal /POR is fixed at the low level and supply voltage VCC reaches a predetermined stable value. Owing to the function of delay circuit 8, power-on detection signal /POR attains the high level when supply voltage VCC is stabilized.
Now, an operation of the power-on detecting circuit shown in FIG. 12 will be described below with reference to a waveform diagram of FIG. 13.
When the power is applied to the semiconductor device, supply voltage VCC on power line 55 rises to the high level. In response to the rise of supply voltage VCC, the potential of node ND1 rises to the high level owing to the capacitive coupling of capacitance 1. Transistors P1 and P2 in inverter circuit 3 are turned off and transistors N1 and N3 are turned on, so that the potential of node ND5 attains the low level. The low level of node ND5 is transmitted through inverter circuit 2 to node ND1. Therefore, even if the potential of node ND1 has risen insufficiently, the latch circuit formed of inverter circuits 3 and 2 carries out the latch operation, whereby the potential of node ND1 is stabilized at the high level.
Meanwhile, the potential of node ND5 is transmitted through inverter circuit 4 to the gates of transistors P3 and N2. Thereby, transistor P3 is turned off and transistor N2 is turned on, so that node ND5 is discharged more strongly to the ground potential.
The potential of node ND2 is transmitted through inverter circuit 5 to delay circuit 8. The output of inverter circuit 5 is currently at the low level. In the delay circuit 8, transistor P4 is turned on, and transistor N8 is turned off. Thereby, node ND3 is charged through transistors P4 and P6. In this operation, transistor P6 functions as the resistor, and thus the potential of node ND3 slowly rises. When the potential of node ND3 becomes higher than a threshold voltage Vth of transistor N10, transistor N10 is turned on, and thus the potential of node ND3 is transmitted to node ND4. Transistor N12 is in the off-state.
When the potential of node ND4 exceeds the threshold voltage of transistor N6 in reset circuit 6, transistor N6 is turned on. Thereby, the high level of node ND1 is discharged to the ground potential level, i.e., low level. The driving capability of transistor N6 is larger than the driving capability of inverter circuit 2. When the potential of node ND1 falls to the low level through the on-state transistor N6, transistors P1 and P2 in inverter circuit 3 are turned on and transistors N1 and N3 are turned off. Thereby, node ND5 is slowly charged by the capacitance 7, and the potential thereof rises to the high level.
When the potential level of node ND5 becomes higher than the input logical threshold voltage of inverter circuit 4, the potential of node ND2 falls to the low level, and correspondingly, power-on detection signal /POR sent from inverter circuit 5 rises to the high level.
In response to the rise of power-on detection signal /POR to the high level, transistors N8 and N12 are turned on and transistor P6 is turned off in delay circuit 8. Thereby, nodes ND3 and ND4 are discharged to the ground potential, i.e., low level, and transistor N6 in reset circuit 6 is turned off.
When the potential level of node ND1 is the low level and the potential of node ND5 exceeds the logical threshold voltage of inverter circuit 2, the latch circuit formed of inverter circuits 2 and 3 functions, to fix the potential of node ND1 at the low level.
In response to the fall of the potential of node ND2, transistor P3 is turned on and transistor N2 is turned off, whereby node ND5 is rapidly charged by transistors P1, P2 and P3.
In the stable state after the power-on, the potential level of node ND1 is the low level, and power-on detection signal /POR is at the high level.
Provision of the capacitance 7 described above slows the rising speed of the potential of node ND5, which achieves the stable latch state of the latch circuit formed of inverter circuits 2 and 3.
Delay circuit 8 activates reset circuit 6 after the elapsing of the predetermined time, utilizing the resistance action of transistors P6 and N10. Thereby, after supply voltage VCC attains the stable state, power-on detection signal /POR rises to the high level, so that erroneous generation of the power-on detection signal, which may be caused in the instable transition state at the power-on, is prevented.
When reset node ND1 is reset at the low level, node ND5 is rapidly charged by the transistors P3 and N2, which quickens the latch operation.
When the power is turned off, the supply voltage VCC of power line 55 falls from the high level to the low level. Node ND1 is already at the low level, and transistor N6 in reset circuit 6 is in the off-state. Therefore, the potential of node ND1 slightly lowers down to a negative potential due to the capacitive coupling by capacitance 1. Transistors P1 and P2 are in the on-state, and transistors N1 and N3 are in the off-state. Therefore, the potential of node ND5 is discharged through transistors P2 and P1 to power supply potential VCC (which lowers to the potential of 0V), and thus the potential of the node ND5 lowers. Also, in response to the fall of supply voltage VCC to the low level, the output of inverter circuit 5 also attains the low level, so that power-on detection signal /POR falls to the low level.
As described above, the conventional power-on detecting circuit uses capacitance 1 for detecting or sensing the power-on. Therefore, when supply voltage VCC falls to the low level (ground potential level) at the power-off, the potential of node ND1 further lowers, as indicated by a dashed line in FIG. 13, from the ground potential level, i.e., low level to the negative potential due to the capacitive coupling! of capacitance 1. Thus, the negative charges remain in node ND1.
Although capacitance 7 is employed for surely inverting the latch state of the latch circuit formed of inverter circuits 2 and 3, positive charges are accumulated in node ND5 of capacitance 7 in the stable state. At the power-off, the positive charges of node ND5 are discharged through transistors P1, P2 and P3 to power line 55. Transistor P3 is turned off when the potential of node ND5 lowers, and the positive charges of node ND5 are ultimately discharged through transistors P2 and P1 to power line 55. The driving power of transistor P2 is not so large and transistors P1 and P2 have the resistance components, so that node ND5 is not sufficiently discharged. Thus, the positive charges remain at node ND5 as shown in FIG. 13(f), and the potential thereof becomes positive.
When the power is applied subsequently to the state in which node ND1 has accumulated the negative charges and node ND5 has accumulated the positive charges, power-on detection signal /POR may not be generated correctly. An operation at the power-on subsequent to the power-off will be described below with reference to FIG. 14.
Upon application of supply voltage VCC, the potential of node ND1 first rises to the high level. After the elapsing of the predetermined time, the reset signal from delay circuit 8 causes the potential of node ND1 to fall to the low level (ground potential level), and correspondingly, the potential of node ND5 rises. In accordance with the rise of the potential of node ND5, power-on detection signal /POR rises from the low level to the high level.
When supply voltage VCC falls to the low level in accordance with the power-off, the potential of node ND1 maintains the negative potential, and the potential of node ND5 maintains the positive potential. In accordance with the lowering of supply voltage VCC to the low level, inverter circuit 5 does not operate any longer, and thus power-on detection signal /POR is slowly discharged.
When supply voltage VCC is raised to the high level subsequently to this state, the potential of node ND1 does not rise to the high level, but rises from the negative potential only to the positive low level. The potential of node ND1 is maintained at the ground potential level by reset circuit 6 after the predetermined time elapses.
When the potential of node ND5 is at high level due to the residual positive charges, the output of inverter circuit 4 attains the low level, and node ND5 is charged to the high level by transistors P1, P2 and P3 in response to the rise of supply voltage VCC to the high level. In response to this charging, power-on detection signal /POR is maintained at the high level immediately after the application of supply voltage VCC, and does not change to the high level after being once fixed at the low level.
Usually, the initializing circuit responds to the transition of power-on detection signal /POR from the low level to the high level by detecting the power-on and carrying out the initializing operation. Therefore, the initializing operation or reset operation in accordance with the power-on cannot be carried out in the initializing circuit, and thus the semiconductor device cannot be set in the stable initial state when the power is applied.
Even if the initializing circuit were constructed to operate in accordance with the high level of power-on detection signal /POR, the reliable initialization or reset operation would not be carried out, because power-on detection signal /POR causes the initializing operation or reset operation under the instable power supply voltage state immediately after the power-on.
If the negative charges remain in node ND1, the potential of node ND1 starts to rise at the power-on due to the capacitive coupling of capacitance 1. However, the potential of node ND1 rises-slowly, because the it rises from the negative potential. Therefore, the current flows through transistors P1 and P2 into node ND5 in response to the power-on, before the potential of node ND1 attains the high level, and thus the potential of node ND5 rises. Node ND5 has accumulated the positive charges. Therefore, the potential of node ND5 attains the high level more rapidly, and the potential of node ND1 is fixed at the low level by inverter circuit 2, so that the effect of the capacitive coupling of capacitance 1 is not fully utilized.